The present invention relates to a polishing slurry and a polishing method using the same, and particularly to a polishing slurry used for chemical-mechanical polishing performed to eliminate steps on a surface to be processed in a process of fabricating a semiconductor device, and a polishing method using the same.
With the trend toward higher densities of devices, the interconnection technique advances toward finer geometries of interconnection and multilayers of interconnection. Such an advance increases and sharpens steps of interlayer insulating films, to thereby degrade processing accuracy and reliability of interconnections formed thereon. That is to say, higher integration of a device may cause degradation of the reliability of the device. Consequently, under the present technical circumstances in which it is difficult to significantly improve step coverage of an aluminum interconnection, it is required to enhance the flatness of an interlayer insulating film.
As the planarization technique of enhancing the flatness of an interlayer insulating film, there has been reported a chemical-mechanical polishing (hereinafter, referred to as "CMP") technique using fine particles of a silicon oxide dispersed in a basic solution. In this polishing method, a surface to be polished of a wafer on which an interlayer insulating film is formed, is planarized by bringing the surface to be polished of the wafer into slide-contact with a polishing plate (or polishing cloth) mounted on a rotating table while supplying slurry on the polishing plate. The slurry is typically composed of an aqueous potassium hydroxide solution in which fine particles of a silicon oxide having an average particle size of about 10 nm are dispersed.
An example of applying the CMP to planarization of an interlayer insulating film has been disclosed by Beppu, Obara and Minamigawa in Journal of Semiconductor World, [1](1994), p. 58-62, published by Press Journal. In this example, a silicon oxide film and an aluminum interconnection layer are sequentially formed on a silicon substrate; the aluminum interconnection layer is patterned by lithography and reactive ion etching (hereinafter, referred to as "RIE"; an interlayer insulating film is formed on the interconnection layer; and projections of the interlayer insulating film are removed by the CMP to finalize planarizing the interlayer insulating film.
In the meantime, an attempt to planarize multilayers of interconnection by polishing has been made by IBM, which has been known as a Damascen process. One example of the process has been reported by S. Roehl et al. in Proc IEEE (Institute of Electrical and Electronics Engineers) Conf. (USA), p. 22-28, (1992). In this technique, an interlayer insulating film is planarized by polishing; a via-contact hole for connecting upper and lower interconnections to each other and a trench into which an upper interconnection layer is to be formed, are formed by etching; and a metal layer is formed on the interlayer insulating film in such a manner that portions of the metal layer are buried in the via-contact hole and the trench; and a region, other than the portions buried in the via-contact hole and the trench, of the metal layer is removed by polishing, to thereby form a buried metal interconnection in the via-contact hole and the trench.
The above technique of applying the CMP to planarization of an interlayer insulating film, however, has the following problem. That is to say, if an interlayer insulating film has only a region in which interconnections are relatively densely arranged, such a region can be polished into a flat shape; however, as shown in FIG. 3, when an interlayer insulating film 114 has both a projecting region A covering an area in which interconnections 113 are densely formed on a silicon oxide film 112 provided on a silicon substrate 111 and a recessed region B covering an area in which no interconnection is formed on the silicon oxide film 112, a polishing plate 121 is deformed upon polishing of the interlayer insulating film 114 (CMP). Accordingly, a stress applied to the region B becomes equal to that applied to the region A. The polishing rate at the region B is thus made nearly equal to that at the region A, which makes it difficult to reduce, by the CMP, a step formed between the regions A and B. This causes a problem that the exposure focal point at the upper portion of the step does not conform to that at the lower portion of the step upon photo-lithography, thereby making it difficult to form a finer interconnection on the step.
To cope with such a problem, as disclosed by INKIKIM in CMP-MIC Conf. (USA), P. 335-338, (1997), there has been made an attempt to reduce deformation of a polishing plate upon polishing by reviewing the material of the polishing plate. However, the use of a material having only a high hardness simply for improving the hardness of the polishing plate causes a high possibility of occurrence of damages called scratches on the surface of a substrate upon CMP. Further, since polishing abrasive grains are supplied to a wafer from the outer peripheral side thereof, they are less supplied to the center of the wafer, there occurs a problem that the polishing rate becomes significantly fast at the peripheral portion as compared with the center of the wafer.